1. Field of the Invention
The present invention relates to an active-matrix liquid crystal display (LCD) device and a method of fabricating the same, and more particularly, to an array substrate having thin film transistors for the active-matrix LCD device and the method of fabricating the array substrate. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a fabrication cost in the LCD device as well as improving a fabrication yield of the LCD device.
2. Discussion of the Related Art
An LCD device uses optical anisotropy to display images. A typical LCD device includes an upper substrate, a lower substrate, and a liquid crystal material interposed therebetween.
FIG. 1 is an exploded perspective view illustrating a typical LCD device 11. The LCD device 11 includes an upper substrate 5 and a lower substrate 22 opposing with each other, and a liquid crystal layer 14 interposed therebetween. The upper substrate 5 and the lower substrate 22 are alternatively called a color filter substrate and an array substrate, respectively. On the upper substrate 5, a black matrix 6 and a color filter layer 7 that includes a plurality of sub-color-filters red (R), green (G), and blue (B) are formed. The black matrix 6 surrounds each sub-color-filter to form an array matrix feature. Further on the upper substrate 5, a common electrode 18 is formed to cover the color filter layer 7 and the black matrix 6.
On the lower substrate 22, opposing the upper substrate 5, a thin film transistor (TFT) “T” is formed as a switching element in the shape of an array matrix corresponding to the color filter layer 7. In addition, a plurality of crossing gate lines 13 and data lines 15 are positioned such that the TFT “T” is located near each crossing portion of the gate lines 13 and the data lines 15, thereby defining a pixel region “P”. In the pixel region “P”, a pixel electrode 17 is disposed and is made of a transparent conductive material, usually indium tin oxide (ITO).
Liquid crystal molecules of the liquid crystal layer 14 are aligned according to electric signals applied by the TFT “T”, thereby controlling incident rays of light to display an image. Specifically, electrical signals applied to the gate line 13 and the data line 15 are transmitted to a gate electrode and a source electrode of the TFT “T”, respectively. The signal applied to the drain electrode is transmitted to the pixel electrode 17 thereby aligning the liquid crystal molecules of the liquid crystal layer 14. Then, rays of back light (not shown) selectively pass through the liquid crystal layer 14 to display an image.
A fabricating process of the above-mentioned array substrate requires repeated steps of depositing and patterning of various layers. The patterning step adopts a photolithography mask step (a masking step) including selective light exposure using a mask (photomask). Since one cycle of the photolithography step is facilitated with one mask, the total number of masks used in the fabrication process is a critical factor in determining the total number of patterning steps. Furthermore, as fabricating processes for the array substrate become more simplified, fabrication errors associated with the fabricating processes may decrease.
It is preferable to reduce the number of masks used for fabricating the array substrate from eight to five. FIG. 2 is a plan view illustrating an array substrate 22 fabricated by applying conventional fabricating processes using five masks. As shown, the array substrate 22 includes a pixel “P” defined by crossing gate line 13 and data line 15. The pixel “P” includes a TFT “T” as a switching element, a pixel electrode 17, and a storage capacitor “C”. The TFT “T” includes a gate electrode 26, a source electrode 28, a drain electrode 30, and an active layer 55. The source electrode 28 electrically connects with the data line 15, whereas the gate electrode 26 electrically connects with the gate line 13. The data line 15 is formed over a silicon line 58 (in FIG. 3C) which is integrally formed with the active layer 55, and the silicon line 58 has a shape similar to the data line 15.
The storage capacitor “C” has a “storage on gate” structure, where a capacitor electrode 16 and a portion of the gate line 13 serve as an upper electrode and a lower electrode, respectively, of the storage capacitor “C”. This configuration of the storage capacitor “C” has a MIM (metal-insulator-metal) structure.
The fabricating processes for the LCD device is determined according to design specifications for the array substrate and/or specific materials selected for the various layers in the array substrate. For example, in case of fabricating a large-scaled (12 inches or larger) LCD, the specific resistance of a material selected for the gate lines is a critical factor in determining the performance quality of the LCD. Therefore, a highly conductive metal such as aluminum (Al) or aluminum alloys are conventionally used for large-scaled LCD devices.
Referring now to FIGS. 3A to 3E, a conventional five masking process and a more detailed description of the structure of the TFT and storage capacitor will be discussed.
For the TFT, an inverted staggered type is advantageously employed because of its simple structure and superior performance quality. The inverted staggered type TFT is classified into two different types, a back-channel-etch type and an etching-stopper type, according to the method used in forming the channel region of the TFT. The back-channel-etch type has a simpler structure than the etching-stopper type. FIGS. 3A to 3E refer to the back-channel-etch type TFT.
First, a substrate 22 is cleaned to remove particles or contaminants on the surface thereof. Then, as shown in FIG. 3A, a first metal layer is deposited on the substrate 22 using a sputtering process. The first metal layer is then patterned using a first mask to form a gate electrode 26 and a gate line 13. As previously mentioned, a portion of the gate line 13 is used as a lower electrode of the storage capacitor “C” of FIG. 2. Aluminum is conventionally used for forming the gate electrode 26 in order to decrease RC delay. However, pure aluminum is considered chemically weak and may result in the formation of hillocks during high-temperature processing. Accordingly, aluminum alloys or layered aluminum structures are used for the gate electrode instead of a pure aluminum.
Next, as shown in FIG. 3B, a gate insulating layer 50 is formed on the substrate 22 to cover the first metal layer including the gate electrode 26 and the gate line 13. Thereafter, an amorphous silicon layer (a-Si:H) and a doped amorphous silicon layer (n+a-Si:H) are sequentially formed on the gate insulating layer 50 and subsequently patterned using a second mask to form an active layer 55, an ohmic contact layer 56, a silicon line 58 and a doped silicon line 60. The ohmic contact layer 56 decreases a contact resistance measured between the active layer 55 and a second metal layer that will be formed in a later step. The silicon line 58 and the doped silicon line 60 have a shape similar to that of the data line 15 (in FIG. 2).
Next, as shown in FIG. 3C, a second metal layer is deposited on the gate insulating layer 50, and patterned using a third mask to form a source electrode 28, a drain electrode 30 and a data line 15. The data line 15 is electrically connected to the source electrode 28 and covers the silicon line 58 and the doped silicon line 60. When the silicon line 58 and the doped silicon line 60 are interposed between the data line 15 and the substrate 22, good adhesion for the data line 15 is achieved. Thereafter, using the source electrode 28 and the drain electrode 30 as masks, a portion of the ohmic contact layer 56 between the source electrode 28 and the drain electrode 30 is etched away.
Since there is no etching selectivity between the ohmic contact layer 56 and the active layer 55, care must be taken in etching the ohmic contact layer 56 between the source electrode 28 and the drain electrode 30. In actuality, about 50 to 100 nm of the active layer 55 is etched away when etching the ohmic contact layer 56. The performance characteristics of the TFT depend directly upon etching uniformity of the over-etched portion in the active layer 55.
Next, as shown in FIG. 3D, an insulating material is deposited and subsequently patterned to form a passivation layer 57. This passivation layer 57 serves to protect the active layer 55. The passivation layer 57 includes at least an inorganic insulating material including silicon oxide (SiO2), a silicon nitride (SiNx), or an organic insulating material including benzocyclobutene (BCB). This materials are selected for use as the passivation layer 57 because of their high light-transmittance, improved water-resistance, and high reliability. The passivation layer 57 is patterned using a fourth mask to form a drain contact hole 31 over the drain electrode 30 and a capacitor contact hole 58 over the capacitor electrode 16. The pixel electrode 17 (in FIG. 3E) contacts the drain electrode 30 via the drain contact hole 31, and contacts the capacitor electrode 16 via the capacitor contact hole 58. Though not shown, a data pad contact hole is also formed over a data pad, which is connected with one end of the data line 15, such that a data pad electrode contacts the data pad via the data pad contact hole.
In FIG. 3E, a transparent conductive material such as indium tin oxide (ITO) is deposited on the passivation layer 57, and patterned using a fifth mask to form the pixel electrode 17. As previously mentioned, the pixel electrode 17 contacts the drain electrode 30 via the drain contact hole 31, and contacts the capacitor electrode 16 via the capacitor contact hole 58.
Therefore, five masks are used during conventional processing for fabricating an array substrate of the LCD device. However, if aluminum is selected for forming the gate electrode, at least two additional masks are needed to prevent the formation of hillocks. Accordingly, at least five masking steps, and as many as seven steps, are required in conventional fabricating processing of the array substrate.
As mentioned previously, decreasing the number of masking steps will decrease the associated manufacturing cost and improve manufacturing yield.